Replacement metal gate process for CMOS integrated circuits

ABSTRACT

A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. Nonprovisional patent application Ser. No. 13/609,621, filed Sep. 11, 2012, the contents of which are herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to complementary metal-oxide-semiconductor (CMOS) integrated circuits having metal-gate transistors with high dielectric constant gate dielectrics.

Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. As is fundamental in the art, reduction in the size of physical feature sizes of structures realizing transistors and other solid-state devices enables greater integration of more circuit functions per unit “chip” area, or conversely, smaller chip area consumed for a given circuit function. The capability of integrated circuits for a given cost has greatly increased as a result of this miniaturization trend.

Advances in semiconductor technology in recent years have enabled the shrinking of device minimum device feature size (e.g., the width of the gate electrode of a metal-oxide-semiconductor (MOS) transistor, which defines the transistor channel length) into the extreme sub-micron range. State of the art transistor channel lengths are now approaching the sub-20 nanometer regime. For MOS transistors, the scaling of transistor feature sizes into the deep submicron realm necessitates the thinning of the MOS gate dielectric layer. Conventional gate dielectric layers (e.g., silicon dioxide) have thus become extremely thin, which can be problematic from the standpoint of gate current leakage, manufacturing yield and reliability. In response to this limitation of conventional gate dielectric material, so-called “high-k” gate dielectrics, such as hafnium oxide (HfO₂), have become popular. These dielectrics have higher dielectric constants than silicon dioxide and silicon nitride, permitting those films to be physically thicker than corresponding silicon dioxide films while remaining suitable for use in high performance MOS transistors. Because these high-k films are currently of lesser quality (from a defect density standpoint) than conventional dielectric material, typical conventional high-k gate dielectrics include both the high-k material and a high quality interface layer of silicon dioxide or the like; the silicon dioxide provides good dielectric integrity and quality, while the high-k material has a sufficiently high dielectric constant to make up for any degradation in electrical performance due to the interface layer.

As also known in the art, gate electrodes of metals and metal compounds, such as titanium nitride, tantalum-silicon-nitride, tantalum carbide, and the like are now also popular in modern MOS technology, especially in combination with high-k gate dielectrics. These metal gate electrodes eliminate the undesired polysilicon depletion effect, which is particularly noticeable at the extremely small feature sizes required of these technologies.

As fundamental in the art, attainment of the desired MOS transistor performance, specifically its threshold voltage, requires tuning of the characteristics of the gate material along with the dopant concentration and other physical parameters of the silicon channel region and source/drain regions. An important parameter in this tuning is the work function of the gate electrode. CMOS integrated circuits complicate this engineering, because the desired gate material work function is necessarily different for n-channel MOS transistors than for p-channel MOS transistors. For polysilicon gate material, this different work function is relatively easy to attain by way of ion implant, for example by exposing each gate electrode to the source/drain implants for its transistor; fine tuning is accomplished by threshold adjust implant to the channel region prior to gate formation.

While post-formation doping of metal gate electrodes has been used to adjust the metal gate work function, conventional high-k metal gate CMOS manufacturing processes often use different gate materials for n-channel and p-channel transistors. The provision of these different gate materials has resulted in structural issues in conventional CMOS integrated circuits, as will now be described in connection with FIGS. 1a through 1 h.

FIG. 1a illustrates, in cross-section, a portion of a high-k metal gate CMOS integrated circuit, partially fabricated according to a conventional process. The structure of FIG. 1a includes many features common to conventional polysilicon-gate CMOS integrated circuits, including p-well 4 p and n-well 4 n formed at the surface of a single-crystal silicon substrate. Isolation dielectric structure 5, for example in the form of a shallow trench isolation (STI) structure, is formed at the surface of the substrate, at the boundary between wells 4 p, 4 n; other instances of isolation dielectric structure 5 will be present in the integrated circuit to isolate separate transistors from one another, including within wells 4 p, 4 n, as known in the art. In the example of FIG. 1a , polysilicon gate structures 8 are disposed over selected locations of wells 4 p, 4 n, namely at the locations at which the eventual transistor gates will be formed, and overlying gate dielectric layer 7. N+ source/drain regions 6 n are heavily-doped regions formed into p-well 4 p on opposing sides of gate structures 8, and p+ source/drain regions 6 p are similarly heavily-doped regions formed into n-well 4 n on opposing sides of gate structures 8. Source/drain regions 6 n, 6 p are formed by conventional ion implantation in a self-aligned manner relative to gate structures 8, and to sidewall dielectric spacers 9 in place along the sides of gate structures 8. In this conventional process, spacers 9 are formed on opposing sides of gate structures 8 to define the eventual gate width of the metal-gate transistor. These spacers 9 themselves, or in combination with additional sidewall spacers, may be used to define lightly-doped-drain source/drain extensions, as known in the art.

In this conventional high-k metal gate technology, gate structure 8 and gate dielectric 7 are “dummy” structures, in that these elements do not become part of the finished integrated circuit. Rather, dummy gate structure 8 and dummy gate dielectric 7 serve as placeholders for defining the placement of source/drain regions 6 n, 6 p, and will be removed. In FIG. 1b , gap fill dielectric material 11 has been formed by chemical vapor deposition (CVD) overall, followed by chemical-mechanical polishing (CMP) to planarize the structure. Gap fill dielectric 11 fills in the spaces between dummy gate structures 8, and will generally remain throughout the formation of the high-k metal gate transistors. Subsequent etches remove dummy gate structures 8 and dummy gate dielectric 7, resulting in the structure of FIG. 1 c.

Referring to FIG. 1d , following the removal of dummy gate structures 8 and dummy gate dielectric 7, this conventional process deposits high-k dielectric 14 (typically overlying a thin interface layer, not shown in FIG. 1d ). High-k dielectric 14 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a material with a relatively high dielectric constant as compared with silicon dioxide or silicon nitride; a typical conventional high-k dielectric material is HfO₂, with other choices for high-k dielectric 14 also known in the art. Metal gate layer 15 p is a layer of a metal or conductive metal compound that by its composition or by doping has a work function suitable for serving as the gate for p-channel MOS transistors with the desired threshold voltage for purposes of this integrated circuit. Examples of metal gate layer 15 p include one or more of palladium, nickel, iridium, ruthenium, tungsten, molybdenum, tungsten nitride, carbonitrides including titanium carbonitride and tantalum carbonitride, oxynitrides, ruthenium oxide, TiAlN, TaCNO, and the like. Typically, a barrier metal layer (not shown) underlies the eventual metal gate layer 15 p, to prevent interdiffusion among the materials. In this conventional process, metal gate layer 15 p is then deposited overall, including over both n-well 4 n at which a p-channel transistor will be formed and over p-well 4 p at which an n-channel transistor will be formed.

Formation of the n-channel transistor is then performed, in this conventional process, by the dispensing and photolithographic patterning of photoresist 17, as shown in FIG. 1e , to protect the locations of the integrated circuit at which p-channel transistors are to be formed (i.e., n-well 4 n) and expose those locations at which n-channel transistors are to be formed. An etch of metal gate layer 15 p from those exposed locations results in the structure of FIG. 1e , with high-k gate layer 14 and any underlying interface layer remaining in place. Photoresist 17 remaining over n-well 4 n is then removed.

Metal gate layer 15 n, composed of a metal or conductive metal compound that by its composition or by doping has a work function suitable for serving as the gate for n-channel MOS transistors with the desired threshold voltage, is then deposited over both p-well 4 p at which an n-channel transistor will be formed, and also over metal gate layer 15 p remaining in place over n-well 4 n. The material of metal gate layer 15 n may consist of one or more elemental metals, ternary metals, metal alloys, and conductive metal compounds. Examples of metal gate layer 15 n include tantalum, titanium, hafnium, and their nitride and carbide compounds; silicon nitride, aluminum nitride, and aluminum silicon nitride compounds; and combinations thereof. Typically, a barrier metal layer (not shown) underlies the eventual metal gate layer 15 n, to prevent interdiffusion among the materials.

Following deposition of metal gate layer 15 n, another barrier layer (not shown) is typically formed, followed by deposition of fill metal 18 overall. Fill metal 18 is intended to fill the remaining interior gap within the eventual gate electrodes of the two transistors. Examples of the conventional composition of fill metal 18 include tungsten, aluminum, and the like. The resulting structure is shown in an idealized representation in FIG. 1g . This structure is then subjected to CMP to remove the excess metal, such CMP typically continuing until the surface of gap fill dielectric material 11 is cleared.

It has been observed, according to this invention, that this conventional process necessarily involves the filling of a very narrow gap within the p-channel transistor gate structure, with fill metal 18. FIG. 1h , which is an inset of FIG. 1 g prior to the deposition of fill metal 18, illustrates this difficulty in additional detail. FIG. 1h shows the large number of layers that fill the space remaining after removal of dummy gate electrode 8 and dummy gate dielectric 7, according to a conventional process. Interface layer 12 is disposed at the bottom of the gate opening, on which high-k gate dielectric 14 is then formed. Barrier metal 16 p is in contact with high-k gate dielectric 14, upon which metal gate layer 15 p (for this p-channel MOS transistor) is then formed. Second barrier metal 16 n is deposited over metal gate layer 15 p, followed by metal gate layer 15 n. Third barrier metal 17 b is then formed over metal gate layer 15 n, prior to the deposition of fill metal 18. As a result of this construction, gap 19 within the p-channel gate structure can be quite narrow, and thus difficult to fill with fill metal 18. This gap 19 has been observed to be sufficiently narrow as to cause problems in step coverage of fill metal 18 (i.e., thinning or opens at the corners of barrier metal layer 17 b), as well as voids within the gate structure itself. Such voids can result in increased resistivity in conduction along the gate electrode, and thus non-uniform potential along the gate electrode for individual transistors, and inconsistencies in operation among a population of transistors.

In addition, the formation of metal gate layers 15 n, 15 p adjacent to one another in the same gate structure raises the risk of interdiffusion of material between the two metals, particularly from the overlying metal gate layer 15 n into the underlying metal gate layer 15 p. Such interdiffusion can change the work function of the intended gate metal (metal gate layer 15 p in the example of FIG. 1h ), and thus degrade the intended transistor performance. Accordingly, barrier metal layer 16 n is necessary between these two metal gate layers, which inserts another layer of metal into the narrowing gap as well as complicating the overall manufacturing process.

By way of further background, commonly owned U.S. Pat. No. 8,062,966, issued Nov. 22, 2011, entitled “Method for Integration of Replacement Gate in CMOS Flow”, and incorporated herein by this reference, describes a high-k metal gate structure and process, according to which CMOS integrated circuits are constructed using a replacement gate process.

BRIEF SUMMARY OF THE INVENTION

Embodiments of this invention provide a high-k metal gate complementary metal-oxide-semiconductor (CMOS) structure and a method of manufacturing the same in which replacement metal gate structures are formed for both transistors with good step coverage and good fill characteristics.

Embodiments of this invention provide such a structure and method in which the risk of interdiffusion between metal gate layers of differing work function is avoided.

Embodiments of this invention provide such a structure and method in which the high-k gate dielectric material can be optimized for both the p-channel MOS transistors and the n-channel MOS transistors in the same CMOS integrated circuit.

Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.

Embodiments of this invention may be implemented into a replacement gate manufacturing process flow for a high-k metal gate CMOS integrated circuit, and the structure formed by such a process, in which the dummy polysilicon gate and dummy gate dielectric structures are removed separately for the n-channel and p-channel MOS transistors relative to one another. The thickness and composition of the high-k gate dielectric material for the n-channel and p-channel MOS transistors, including any required interface layer between the underlying silicon and the high-k material, can be independently controlled in order to optimize the reliability and performance separately for the transistors of each conductivity type.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1a through 1h are cross-sectional views of an integrated circuit at various stages of manufacture according to a conventional manufacturing process flow.

FIG. 2a is a plan view, and FIG. 2b is a cross-sectional view, of a complementary metal-oxide-semiconductor (CMOS) integrated circuit structure constructed according to embodiments of the invention.

FIGS. 3a through 31 are cross-sectional views of the integrated circuit of FIGS. 2a and 2b at various stages of manufacture, according to embodiments of this invention.

DETAILED DESCRIPTION OF THE INVENTION

This invention will be described in connection with its embodiments, namely as implemented into a complementary metal-oxide-semiconductor (CMOS) integrated circuit, as it is contemplated that the invention will be especially beneficial in such an application. However, it is further contemplated that this invention can be beneficially applied to other integrated circuit structures and processes. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.

FIGS. 2a and 2b illustrate, in plan and cross-sectional views, respectively, the construction of p-channel MOS transistor 20 p and n-channel MOS transistor 20 n, both constructed in a CMOS integrated circuit according to embodiments of this invention. While these Figures show transistors 20 n, 20 p located adjacent to one another, it is of course contemplated that these transistors 20 n, 20 p may be located at a larger distance from one another, and need not necessarily have an electrical relationship with one another. In addition, as fundamental in the art, many n-channel and p-channel transistors constructed similarly as transistors 20 n, 20 p described herein will typically be constructed within the same integrated circuit, varying in size (channel width, channel length, etc.) and shape of those transistors according to the layout and desired electrical characteristics.

In this example, transistor 20 n is constructed within an instance of p-type well 24 p and transistors 20 p is constructed within an instance of n-type well 24 n. According to a twin-well process, wells 24 p, 24 n are each well regions formed by way of ion implant into a single-crystal silicon substrate. Wells 24 n, 24 p, and also individual transistors within the same well, are generally isolated and separated from one another at the surface by an instance of isolation dielectric structure 25 (FIG. 2b ). In this example, isolation dielectric structure 25 is constructed as a shallow trench isolation (STI) structure, consisting of a deposited dielectric material (e.g., silicon nitride or silicon dioxide) disposed into a trench etched into selected locations of the surface. Alternatively, isolation dielectric structure 25 may be formed of thermal silicon dioxide of a type constructed according to the well-known local-oxidation-of-silicon (LOCOS) process.

Alternatively, in the case of the CMOS integrated circuit being fabricated according to a single-well process, only one of wells 24 p, 24 n will be formed. For the example in which the substrate is p-type silicon, transistor 20 n would be constructed into a surface portion of the substrate itself rather than into an instance of a separately formed p-type well. Further in the alternative, transistors 20 n, 20 p may be constructed within a surface silicon layer overlying an insulator layer, according to the well-known silicon-on-insulator (SOI) technology. In that case, wells 24 n, 24 p would be formed of doped regions of that silicon layer, with the doping typically extending throughout the thickness of that layer.

As shown in FIGS. 2a and 2b , transistors 20 n, 20 p each include respective metal gate structures 30 n, 30 p overlying selected portions of wells 24 p, 24 n, respectively. The construction of metal gate structures 30 n, 30 p will be described in further detail below. In n-channel transistor 20 n, heavily-doped n-type source/drain regions 26 n are disposed into the surface of p-well 24 p on opposing sides of metal gate structure 30 n, and constitute the source and drain regions of transistor 20 n. Similarly, p-channel transistor 20 p includes heavily-doped p-type source/drain regions 26 p disposed on either side of metal gate structure 30 p, at the surface of n-well 24 n.

As will be described in detail below, metal gate structures 30 n, 30 p are formed according to a “replacement gate” process. As such, gap fill dielectric material 31 is disposed over the surface of source/drain regions 26 n, 26 p and isolation dielectric structure 25, at a thickness corresponding to the thickness of metal gate structures 30 n, 30 p (FIG. 2b ). As evident from the plan view of FIG. 2a , contact openings 29 are formed through gap fill dielectric material 31 at selected locations of source/drain regions 26 n, 26 p, to allow subsequently deposited and patterned conductors to make electrical contact to transistors 20 n, 20 p.

Referring specifically to FIG. 2b , metal gate structure 30 n is a laminated structure of several different physical layers. Metal gate structure 30 n includes (or overlies, as the case may be) interface dielectric layer 32 n, which is in contact with the surface of p-well 24 p, at the bottom of metal gate structure 30 n and between dielectric spacers 29. Interface layer 32 n may be constructed of a thermal silicon dioxide, in which case its location is constrained to the surface of p-well 24 p. Alternatively, interface layer 32 n may be a deposited dielectric film (e.g., deposited silicon nitride, deposited silicon dioxide, or combination thereof), in which case interface layer 32 n would generally be present along the sides of spacers 29.

Deposited high-k gate dielectric 34 n overlies interface layer 32 n, and in this embodiment of the invention is also present on the sides of spacers 29. High-k gate dielectric 34 n is constructed of a dielectric material with a relatively high dielectric constant as compared with silicon dioxide or silicon nitride; typical high-k dielectric materials suitable for use as high-k gate dielectric 34 n include hafnium oxide (HfO₂), hafnium zirconium oxide (HfZrO_(x)), and combinations of high-k materials, such as hafnium oxide in combination with zirconium oxide (e.g., HfO₂/ZrO₂ and ZrO₂/HfO₂). Other high-k dielectric materials known in the art may alternatively be used in embodiments of this invention.

The use of interface layer 32 n in combination with high-k gate dielectric 34 n in the construction of high-k metal gate transistors is well known in the art. Using current-day technology, high-k gate dielectric materials typically have a relatively high defect density as compared with high quality silicon dioxide and silicon nitride films. Accordingly, the use of only a high-k material as the gate dielectric of a MOS transistor would result in undesired gate leakage, and degraded transistor reliability. As known in the art, the effects of these defects in high-k gate dielectric materials can be minimized by constructing the transistor gate dielectric as a combination of the high-k dielectric material and a high quality interface layer of silicon dioxide or silicon nitride. The dielectric constant of the high-k material is contemplated to be sufficiently high that the additional series capacitance presented by the interface layer will not unduly reduce the effective capacitance of the combination to such an extent that the desired transistor and circuit performance goals cannot be met.

Overlying high-k gate dielectric 24 n within metal gate structure 30 n is a relatively thin layer of barrier metal 36 n, above which metal gate layer 35 n is disposed. Barrier metal 36 n is provided to limit interdiffusion between metal gate layer 35 n and high-k gate dielectric 24 n, as known in the art. The composition of barrier metal 36 n depends on the particular materials of the layers on either side, but is typically a metal from the lanthanide series (e.g., lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, ytterbium), or a conductive metal compound thereof (e.g., lanthanum oxide). Metal gate layer 35 n consists of an elemental metal, ternary metal, metal alloy, or conductive metal compound that is selected or doped to have a work function suitable for the desired electrical parameters (i.e., threshold voltage) of n-channel transistor 20 n. Examples of suitable materials for metal gate layer 35 n include tantalum, titanium, hafnium, zirconium, tungsten, molybdenum, and their nitride and carbide compounds; silicon nitride, aluminum nitride, and aluminum silicon nitride compounds; and combinations thereof.

Barrier metal 37 n overlies metal gate layer 35 n, and is provided to limit interdiffusion between metal gate layer 35 n and overlying fill metal 38 n. Examples of the material of barrier metal 37 n include titanium nitride and tantalum nitride; other materials known in the art may alternatively be used as barrier metal 37 n according to embodiments of this invention. Fill metal 38 n completes metal gate structure 30 n according to this embodiment of the invention, and is provided as a conductor that fills the interior of the gap between adjacent instances of gap fill dielectric 31. Examples of materials suitable for fill metal 38 n include tungsten, aluminum, alloys thereof, and other conventional metals and materials that serve as conductors in modern integrated circuits.

Metal gate structure 30 p is somewhat similarly constructed as metal gate structure 30 n, with some differences in composition as will be described below. As in the case of metal gate structure 30 n, metal gate structure includes or overlies interface dielectric layer 32 p at the surface of n-well 34 n, between dielectric spacers 29. Interface layer 32 p may be constructed of the same material as interface layer 32 n, or may alternatively be constructed from a different material; if of a different material, it is contemplated that the material of interface layer 32 p will be selected from one of the materials listed above for interface layer 32 n. Further in the alternative, interface layer 32 p may be present along the sides of spacers 29, if it is a deposited film rather than a thermal film. High-k gate dielectric 34 p overlies interface layer 32 p, and extends along the sides of spacers 29 (and interface layer 32 p, if present). High-k gate dielectric 34 p may be constructed of the same material as high-k gate dielectric 34 n, or may be composed of a different material if desired; if of a different material, it is contemplated that the material of high-k gate dielectric 34 p will be selected from one of the materials listed above for high-k gate dielectric 34 n.

According to embodiments of this invention, the thicknesses and composition of interface layer 32 p and high-k gate dielectric 34 p may differ from their counterpart films of interface layer 32 n and high-k gate dielectric 34 n. For example, it may be preferable for one of n-channel transistor 20 n and p-channel transistor 20 p to have a thinner effective gate dielectric than the other, in order to match or otherwise optimize device performance. Alternatively or in addition, differences in the particular materials used within metal gate structures 30 n, 30 p may motivate the selection of different thicknesses or materials for the respective gate dielectrics of transistors 20 n, 20 p. For the example illustrated in FIG. 2b , in one embodiment of the invention, interface layer 32 n of transistor 20 n is significantly thicker than interface layer 32 p of transistor 20 p, while high-k dielectric 34 n of transistor 20 n is significantly thinner than interface layer 34 p of transistor 20 p. In one example corresponding to the cross-section of FIG. 2b , in which transistors 20 p, 20 n have a nominal channel length of 15 to 40 nm and effective gate dielectric thicknesses (i.e., silicon dioxide equivalent) of between 1 and 2 nm, the composition and thicknesses of these materials are:

Composition Thickness Interface layer 32n SiO₂ or SiON 10 to 20 Å High-k gate dielectric 34n HfZrO_(x), HfO₂/ZrO₂, or 10 to 30 Å ZrO₂/HfO₂ Interface layer 32p SiO₂ or SiON  5 to 15 Å High-k gate dielectric 34p HfO₂ 15 to 35 Å In this example, the thinner high-k dielectric 34 n (e.g., of HfZrO_(x)) is contemplated to reduce positive bias temperature instability (PBTI) of transistor 20 n over time, while the thicker HfO₂ high-k gate dielectric 34 p is contemplated to reduce negative bias temperature instability (NBTI) of p-channel transistor 20 p over time. It is contemplated that, in many implementations, interface layer 32 n of n-channel transistor 20 n will be thicker than interface layer 32 p of p-channel transistor 20 p while high-k dielectric layer 34 n of n-channel transistor 20 n will be thinner than high-k dielectric layer 34 p of p-channel transistor 20 p. That tendency is reflected in the table above. Other combinations of composition and thickness for these films are also contemplated.

Similarly as in metal gate structure 30 n, a relatively thin layer of barrier metal 36 p overlies high-k dielectric layer 34 n, and metal gate layer 35 p is disposed over that barrier metal 36 p. The composition and thickness of barrier metal 36 p may be the same as barrier metal 36 n, but may differ depending on the requirements caused by differences in the composition and thickness between metal gate layers 35 n and 35 p. Examples of materials suitable for use as metal gate layer 35 according to embodiments of this invention include one or more of palladium, nickel, iridium, ruthenium, tungsten, molybdenum, tungsten nitride, carbonitrides including titanium carbonitride and tantalum carbonitride, oxynitrides, ruthenium oxide, TiAlN, TaCNO, and the like. As discussed above, the material or doping, or both, of metal gate layers 35 n, 35 p will be separately selected for p-channel and n-channel MOS transistors 20 p, 20 n so as to have the desired work function, based on the desired threshold voltages for those devices. These differences in composition of metal gate layers 35 n, 35 p from one another may necessitate differences in the composition and thickness of associated barrier metal layers 36 n, 36 p to optimize their barrier properties for the particular mobile ions presented by respective metal gate layers 35 n, 35 p. The thicknesses of metal gate layers 35 n, 35 p (and barrier metal layers 36 n, 36 p) may differ from one another as well, depending on deposition and other manufacturing factors.

As in the case of metal gate structure 30 n, barrier metal 37 p overlies metal gate layer 35 p, and is provided to limit interdiffusion between metal gate layer 35 p and overlying fill metal 38 p. The composition and thickness of barrier metal 37 p may be the same as, or may differ from, barrier metal 37 n, as appropriate for the particular composition of metal gate layer 35 p. Fill metal 38 p, which is typically of the same composition as fill metal 38 n, completes metal gate structure 30 p and serves as a conductor in the resulting integrated circuit.

According to embodiments of this invention, as particularly evident from FIG. 2b , the CMOS integrated circuit structure including transistors 20 n, 20 p enables the formation of both n-channel and p-channel high-k metal gate MOS transistors of optimized performance using a replacement gate process, while still facilitating the metal fill of both metal gate structures. More specifically, this structure is fabricated without requiring that the metal gate structure of one of the transistor channel conductivity types receive both metal gate layers. As a result, both n-channel and p-channel transistors can be formed at minimum feature size dimensions. Furthermore, according to embodiments of this invention, the composition and thicknesses of both the metal gate materials and also the high-k gate dielectric layers can be selected and optimized for transistors of both channel conductivity types, independently from the composition and thicknesses of those films selected for the other channel conductivity type transistor. Barrier metal layers suitable for the materials of each transistor construction can also be independently selected and optimized, without undue narrowing of the gap fill space in the replacement gate process.

Referring now to FIGS. 3a through 31, a method of constructing the CMOS integrated circuit structure of FIG. 2b , including n-channel MOS transistor 20 n and p-channel MOS transistor 20 p, according to embodiments of this invention will now be described in detail. This description begins with the integrated circuit structure in the form shown in FIG. 3a , in which the structure includes features common to conventional polysilicon-gate CMOS integrated circuits. In this example, p-well 24 p and n-well 24 n are formed at the surface of a single-crystal silicon substrate. As such, the manufacturing process flow according to this embodiment of the invention is a twin-well process, in which wells 24 of both conductivity types are formed by conventional ion implantation processes. Alternatively, this CMOS structure may be fabricated according to a single-well process flow, in which case only either p-well 24 p or n-well 24 n is formed into a substrate of the opposite conductivity type, and in which MOS transistors of the appropriate channel conductivity type are formed at selected locations of that substrate. Further in the alternative, it is contemplated that this invention may be implemented in other types of semiconductor bodies, for example in a single-crystal semiconductor layer overlying an insulator layer according to the well-known silicon-on-insulator (SOI) technology. These and other implementation environments are contemplated to be within the scope of the claims in this case.

Isolation dielectric structure 25 extends into the substrate from its surface, at a boundary between p-well 24 p and n-well 24 n. In this example, as described above relative to the structure 5 of FIGS. 1a through 1h , isolation dielectric structure 25 is composed of silicon dioxide, deposited into an etched trench according to the well-known shallow trench isolation (STI) technology. Other instances of isolation dielectric structure 25 will of course be present, at those locations at which electrical isolation of surface elements is desired. As shown in FIG. 3a , gate dielectric layer 42 is disposed at locations of each of n-well 24 p, 24 n, with an instance of polysilicon gate structure 40 disposed over each. Gate dielectric 42 may be silicon dioxide or silicon nitride, or a combination of the two, or may consist of some other material given its function as essentially a placeholder. Gate dielectric layer 42 may extend over the full surface of the substrate, or may have been removed in the etch forming the gate structures as shown in the example of FIG. 3a . Polysilicon gate structures 40 overlie gate dielectric 42 at the locations at which the eventual metal transistor gate structures will be formed. Sidewall dielectric spacers 29 are disposed on the sides of gate structures 40. Dielectric spacers 29 may be formed of any suitable dielectric material, such as silicon dioxide or silicon nitride, and in the conventional manner by way of chemical vapor deposition and anisotropic etch. Spacers 29 serve to define the width and location of the gate structures in this replacement gate process, as will become apparent from this description.

At the stage of manufacture shown in FIG. 3a , the source and drain regions of the transistors are formed at the desired locations. N+ source/drain regions 26 n are implanted doped regions formed into p-well 24 p on opposing sides of gate structure 40 in the well-known self-aligned manner; similarly, p+ source/drain regions 26 p are implanted doped regions formed into n-well 24 n, self-aligned with gate structure 40 in that location. Spacers 29 themselves, or in combination with additional sidewall spacers, may be used to define lightly-doped-drain source/drain extensions of source/drain regions 26 n, 26 p, in the well-known manner.

The structure of FIG. 3a is fabricated according to conventional manufacturing processes for polysilicon gate CMOS integrated circuits, with the possible exception that spacers 29 may be added structures in those processes in which lightly-doped drain extensions are not formed, or are formed independently of those spacers 29. Gate structures 40 and gate dielectric 42 will be removed in the formation of high-k metal gate transistors 20 n, 20 p, and as such are “dummy” structures serving as a placeholder, and for placement and definition of source/drain regions 26 n, 26 p.

Following the construction of dummy gate structures 40 and sidewall dielectric spacers 29, gap fill dielectric material 31 is deposited over the structure by chemical vapor deposition (CVD); chemical-mechanical polishing (CMP) of gap fill dielectric 31 is then performed to planarize the structure, as shown in FIG. 3b . Gap fill dielectric 31 is composed of silicon dioxide, silicon nitride, or some other suitable dielectric material adequate to withstand subsequent processes, and to isolate the various conductive layers from one another. Following planarization of gap fill dielectric 31, photoresist 44 (FIG. 3c ) is dispensed, patterned, and developed to protect dummy gate structure 40 in the locations at which n-channel transistor 20 n will be formed (and, of course, the locations of other n-channel high-k metal gate transistors), exposing dummy gate structure 40 at the location of transistor 20 p. A polysilicon etch is then performed to remove dummy gate structure 40 where exposed, followed by an etch of dummy gate dielectric 42 at the locations exposed by photoresist 44. The resulting structure is illustrated in FIG. 3c . Photoresist 44 may then be removed from the structure, in advance of the subsequent processes.

Upon clearing the surface of p-well 24 n from which dummy gate structure 40 and dummy gate dielectric 42 were removed, the high-k gate material of transistor 20 p can be formed, the result of which is shown in FIG. 3d . According to embodiments of this invention, interface layer 32 p is first formed, either by thermal oxidation of silicon to form silicon dioxide, or by chemical vapor deposition of silicon dioxide, silicon nitride, or another suitable dielectric material. The example of FIG. 3d illustrates interface layer 32 p as thermal silicon dioxide, and as such interface layer 32 p does not form on the sides of spacers 29; alternatively, a deposited material would form on the sides of spacers 29 as well as the top surface of gap fill dielectric 31 and other structures. Following the formation of interface layer 32 p, high-k gate dielectric 34 p is deposited overall. The particular material of high-k gate dielectric 34 p may be hafnium oxide, or one of the other materials specified above in connection with FIG. 2 b.

Also as discussed relative to FIG. 2b , the composition and thicknesses of interface layer 32 p and high-k gate dielectric 34 p can be selected to optimize the performance, reliability, and other characteristics of p-channel transistor 20 p, independently from n-channel transistor 20 n. For example, interface layer 32 p of thermal silicon dioxide can be relatively thin, while high-k gate dielectric 34 p can be made relatively thick.

Following the formation of high-k gate dielectric 34 p, barrier metal 36 p and metal gate layer 35 p can then be formed by sputtering or another appropriate method, resulting in the structure shown in FIG. 3e . As discussed above relative to FIG. 2b , the composition and thicknesses of barrier metal 36 p and metal gate layer 35 p are selected to have the desired work function for p-channel transistor 20 p, along with a suitable barrier to interdiffusion between high-k gate layer 34 p and metal gate layer 35 p.

Referring now to FIG. 3f , barrier metal 37 p and fill metal 38 p are next formed overall, typically by way of sputter deposition. As discussed above, barrier metal 37 p limits interdiffusion between fill metal 38 p and underlying layers, and as such typically is a relatively thin layer. Fill metal 38 p is intended to fill the remaining gap within the gate structure for transistor 20 p, and as such is typically overfilled by a substantial margin, as shown in FIG. 3f . However, it is contemplated that the gap within the metal gate structure into which fill metal 38 p is sputtered will be sufficiently wide, with only the single level of metal gate layer 35 p therein, to minimize step coverage difficulties and voiding. Following the deposition of fill metal 38 p, CMP is performed to planarize the structure to a level sufficient to expose dummy polysilicon gate 40 at the location of eventual transistor 20 n, as shown in FIG. 3g . This CMP process may thin fill dielectric 31 and the metal gate structure of transistor 20 p to some slight extent, but any such thinning is contemplated to be minimal using conventional control mechanisms.

Following the CMP of fill metal 38 p, dummy gate structure 40 and dummy gate dielectric 42 are removed from the location of transistor 20 n, by way of respective etch processes, resulting in the structure shown in FIG. 3h . Once the surface of p-well 24 p between spacers 29 is clear, interface layer 32 n is formed by thermal oxidation of the silicon at that surface, or by deposition of the desired dielectric material, resulting in the structure of FIG. 3i . Because it is separately formed, interface layer 32 n need not be same material or thickness as interface layer 32 p. Rather, the composition and thickness of interface layer 32 n can be independently selected to optimize the performance and reliability of transistor 20 n. In the example of FIG. 3i , interface layer 32 n is a thermal oxide, formed to a greater thickness than that of interface layer 32 p. High-k gate dielectric 34 n is then deposited overall, as shown in FIG. 3j . As discussed above, high-k gate dielectric 34 n may have a different composition and thickness from that of high-k gate dielectric 34 p, with those properties selected to optimize the performance and reliability of transistor 20 n independently from that of transistor 20 p. In any case, high-k gate dielectric 34 n consists of a high dielectric constant insulating material, such as hafnium oxide. In the example shown in FIG. 3j , high-k gate dielectric 34 p is thinner than high-k gate dielectric 34 n.

As shown in FIG. 3k , barrier metal 36 n and metal gate layer 35 n are then formed by sputtering or another appropriate method over high-k gate dielectric 34 n. The composition and thickness of metal gate layer 35 n are selected to have the desired work function for n-channel transistor 20 p, and as such will typically be a different material or at least have a different doping from that of metal gate layer 35 p. The composition and thickness of barrier metal 36 n are selected to provide a barrier to interdiffusion between high-k gate layer 34 n and metal gate layer 35 n, and may be different from that of barrier metal 36 p, particularly if metal gate layer 35 n is of a different composition than metal gate layer 35 p.

Barrier metal 37 n and fill metal 38 n are then formed overall, again by way of sputter deposition. The resulting structure is illustrated in FIG. 31. The composition of barrier metal 37 p is selected to prevent interdiffusion between fill metal 38 n and underlying layers, and will be typically relatively thin. Fill metal 38 n will typically be of the same material as fill metal 38 p, but may alternatively be of a different metal or metal compound if desired. The sputtering of fill metal 38 n overfills the gap within the gate structure of transistor 20 n, as suggested by FIG. 31. As in the case of transistor 20 p discussed above, this gap within metal gate structure 30 n is relatively wide, especially as compared with that of conventional processes in which the second replacement metal gate structure to be formed includes both metal gate layers. With such a wide gap, fill metal 38 n can be sputtered with good step coverage at the corners, and without significant risk of voiding within the interior of gate structure 30 n. Following the deposition of fill metal 38 n, CMP is performed to planarize the structure, thus completing the construction of transistors 20 n, 20 p, and resulting in the structure shown in FIG. 2b , and described above.

According to embodiments of this invention, a CMOS integrated circuit structure incorporating high-k metal gate MOS transistors, and a process of fabricating the same according to a replacement gate approach, are provided that avoids vulnerabilities caused by the deposition of fill metal into a narrowed gap in the interior of a metal gate structure that includes multiple metal gate layers. This structure and method thus produces a CMOS integrated circuit of improved performance and reliability, and also enables construction of transistors of both conductivity types to the smallest dimensions available for a given technology node. In addition, by avoiding the inclusion of both metal gate layers within the same gate structure, sufficient room remains to include barrier metal layers where appropriate, further enhancing the reliability of the structure. Embodiments of this invention also enable the selection of the composition and thicknesses of metal gate materials and high-k gate dielectric layers for transistors of both channel conductivity types, allowing independent optimization of the performance and reliability of all transistors in the CMOS structure without requiring trade-offs between the transistor types.

While this invention has been described according to its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein. 

What is claimed is:
 1. A method of forming an integrated circuit structure at a semiconducting surface of a body, the integrated circuit structure including first and second transistors of opposite channel conductivity types, comprising: forming first and second dummy gate electrodes overlying a dummy gate dielectric material on the semiconducting surface, the second dummy gate electrode overlying a region of a first conductivity type, and the first dummy gate electrode overlying a region of a second conductivity type, the second conductivity type opposite the first conductivity type; forming source/drain regions of the first conductivity type into the region of second conductivity type, at locations on opposite sides of the first dummy gate electrode; forming source/drain regions of the second conductivity type into the region of first conductivity type, at locations on opposite sides of the second dummy gate electrode; depositing filler dielectric between the first and second dummy gate electrodes; patterning a mask layer over the second dummy gate electrode, the mask layer exposing the first dummy gate electrode; removing the first dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of second conductivity type; forming a first dielectric interface layer at the exposed portion of the region of second conductivity type; depositing a first high-k dielectric layer overall; then depositing a first metal gate layer, the first metal gate layer comprising a metal or metal compound; then depositing a first fill metal to fill the gap at the location from which the first dummy gate electrode was removed; then performing a first chemical-mechanical polishing (CMP) to remove portions of the first fill metal and first metal gate layer and planarize the integrated circuit structure to expose a top surface of the second dummy gate electrode; removing the second dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of first conductivity type; forming a second dielectric interface layer at the exposed portion of the region of first conductivity type; depositing a second high-k dielectric layer overall; then depositing a second metal gate layer, the second metal gate layer comprising a metal or metal compound; then depositing a second fill metal to fill the gap at the location from which the second dummy gate electrode was removed; and then performing a second CMP to planarize the integrated circuit structure and to expose top surfaces of the first and second fill metal and of the filler dielectric; wherein the first metal gate layer and the second metal gate layer differ from one another in composition with the second metal gate layer being removed from over the first transistor and the first metal gate layer being removed from over the second transistor.
 2. The method of claim 1, wherein the first high-k dielectric layer is of a different dielectric material than the second high-k dielectric layer.
 3. The method of claim 2, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer.
 4. The method of claim 1, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer.
 5. The method of claim 4, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer.
 6. The method of claim 5, wherein the first conductivity type is n-type; wherein the second conductivity type is p-type; wherein the first dielectric interface layer is thicker than the second dielectric interface layer; and wherein the first high-k dielectric layer is thinner than the second high-k dielectric layer.
 7. The method of claim 1, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer.
 8. The method of claim 1, further comprising: after the step of removing the first dummy gate electrode and its underlying dummy gate dielectric material and before the step of forming the first dielectric interface layer, removing the mask layer.
 9. The method of claim 1, further comprising: after the step of depositing the first high-k dielectric layer and before the step of depositing the first metal gate layer, depositing a first barrier layer; and after the step of depositing the second high-k dielectric layer and before the step of depositing the second metal gate layer, depositing a second barrier layer.
 10. The method of claim 1, further comprising: after the step of depositing the first metal gate layer and before the step of depositing the first fill metal, depositing a third barrier layer; and after the step of depositing the second metal gate layer and before the step of depositing the second fill metal, depositing a fourth barrier layer.
 11. A method of forming an integrated circuit, comprising: forming first and second dummy gate electrodes overlying a dummy gate dielectric material on a substrate, the second dummy gate electrode overlying a region of a first conductivity type, and the first dummy gate electrode overlying a region of a second conductivity type, the second conductivity type opposite the first conductivity type; depositing filler dielectric between the first and second dummy gate electrodes; removing the first dummy gate electrode and its underlying dummy gate dielectric material to define a first gap between filler dielectric structures over the region of second conductivity type; forming a first dielectric interface layer in the first gap; depositing a first high-k dielectric layer overall; then depositing a first metal gate layer, the first metal gate layer comprising a metal or metal compound; then depositing a first fill metal to fill the gap at the location from which the first dummy gate electrode was removed; then performing a first chemical-mechanical polishing (CMP) to remove portions of the first fill metal and first metal gate layer to expose a top surface of the second dummy gate electrode and planarize a surface of the integrated circuit; then removing the second dummy gate electrode and its underlying dummy gate dielectric material to define a second gap between filler dielectric structures over the region of first conductivity type; forming a second dielectric interface layer in the second gap; depositing a second high-k dielectric layer overall; then depositing a second metal gate layer, the second metal gate layer comprising a metal or metal compound; then depositing a second fill metal to fill the gap at the location from which the second dummy gate electrode was removed; and then performing a second CMP to remove portions of the second fill metal and second metal gate layer to expose top surfaces of the first and second fill metal and of the filler dielectric and planarize a surface of the integrated circuit; wherein the first metal gate layer and the second metal gate layer differ from one another in composition.
 12. The method of claim 11, wherein the first high-k dielectric layer is of a different dielectric material than the second high-k dielectric layer.
 13. The method of claim 11, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer.
 14. The method of claim 13, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer.
 15. The method of claim 14, wherein the first conductivity type is n-type; wherein the second conductivity type is p-type; wherein the first dielectric interface layer is thicker than the second dielectric interface layer; and wherein the first high-k dielectric layer is thinner than the second high-k dielectric layer.
 16. The method of claim 11, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer.
 17. The method of claim 11, further comprising: after the step of depositing the first high-k dielectric layer and before the step of depositing the first metal gate layer, depositing a first barrier layer; and after the step of depositing the second high-k dielectric layer and before the step of depositing the second metal gate layer, depositing a second barrier layer.
 18. The method of claim 11, further comprising: after the step of depositing the first metal gate layer and before the step of depositing the first fill metal, depositing a third barrier layer; and after the step of depositing the second metal gate layer and before the step of depositing the second fill metal, depositing a fourth barrier layer. 